Monday, October 1, 2012
Got up at seven-thirty in the morning. Ate a bowl of noodle soup for lunch. Went out shopping at a grocery store this evening. Ate pieces of Central Market's pizza for dinner.
The idea of 'Moderately doped channel multiple-FinFET for logic applications' occurred to me in the autumn of 2004. Those days, I restarted applying for some patents on semiconductor devices after a five-year interval because of the change in my job responsibilities. 'Moderately doped channel multiple-FinFET for logic applications' was one of my own ideas.
Obviously, it's based on the conventional FinFET, which is a three-dimensional SOI MOSFET reported by the other author previously. I made a brief study on both the undoped-channel fully-depleted SOI and the doped-channel fully-depleted SOI MOSFETs and their device modeling in 1995. The concept of tuning the work functions of the metal gates in order to lower the channel doping for the SOI devices occurred to me when I was working on the transistor optimization of a MOSFET with a high-k gate dielectric and metal gate stacks for logic applications in the spring of 2004. My work on a MOSFET with a high-k gate dielectric and metal gate stacks itself was a sort of repletion with a few new viewpoints for the development of its next technology generation. I identified the concept of using multiple fins to keep the effective gate width wider for the improvements of the performance of the logic circuit and the immunity against the Vt scattering due to random dopant fluctuations in the channel in the autumn of 2004.
One of the purposes of that invention was the correction of a misstep by a group, possibly due to some miscommunication or something else, by way of precaution. The other was a trial to pursue the idealism of how the ideas and the rights of an individual can be protected in an organization. To tell the truth, I told those purposes to one of the coauthors of the technical paper entitled 'Moderately doped channel multiple-FinFET for logic applications' when I started filing for a patent on it in 2004.
Unfortunately, I was unable to patent the device design of 'Moderately doped channel multiple-FinFET for logic applications', though the difficulty in obtaining a patent on it seemed to be less than that in Intel's obtaining the patents on 'Tri-Gate' and 'SiGe S/D Stressor' because of more distinct differences of it from the existing inventions. Contrary to its patent acquisition, the publication of the technical paper for it was successful. For the same purpose as above, the detailed study on that device was presented by me at the International Electron Devices Meeting in Washington DC in 2005, after all approvals necessary for disclosing all the contents described in it to the public were obtained.
PS: My job responsibilities included the invention of new devices as a part in 1997 and 1998. From 1999 until 2003, my job responsibility wasn't oriented toward the invention of new devices, but it was mostly oriented toward the analysis of the device physics, the optimization of the device structure, and the support of the device developments as a team member.
Tuesday, October 2, 2012
Got up at eight o'clock in the morning. Ate a bowl of rice porridge for lunch, and a Japanese meal for dinner.
Wednesday, October 3, 2012
Got up at eight o'clock in the morning. Ate a bowl of noodle soup for lunch, and a dish of Italian pasta for dinner.
Thursday, October 4, 2012
Got up at eight-fifteen in the morning. Ate a bowl of rice porridge for lunch, and a Japanese meal for dinner.
Friday, October 5, 2012
Got up at eight o'clock in the morning. Ate a bowl of noodle soup for lunch, and a Western-Japanese meal for dinner.
Saturday, October 6, 2012
Got up at nine o'clock in the morning. Ate a bowl of rice porridge for lunch. Looked after the front- and backyards of our house this afternoon. Ate a dish of Italian pasta for dinner. Stayed at home for the entire day.
Sunday, October 7, 2012
Got up at ten o'clock. Ate a sandwich for lunch, and an Oriental meal for dinner. It's chilly today. Stayed at home for the entire day.
Monday, October 8, 2012
Got up at eight-thirty in the morning. Ate a bowl of rice porridge for lunch, and a Japanese-Western meal for dinner. Went out shopping at a grocery store this evening.
Tuesday, October 9, 2012
Got up at seven forty-five in the morning. Ate a bowl of noodle soup for lunch, and pieces of California Pizza Kitchen's pizza for dinner.
Wednesday, October 10, 2012
Got up at seven forty-five in the morning. Ate a bowl of rice porridge for lunch, and a dish of Italian pasta for dinner.
Thursday, October 11, 2012
Got up at seven forty-five in the morning. Ate a bowl of noodle soup for lunch, and a Japanese meal for dinner. There were heavy rains today.
Friday, October 12, 2012
Got up at seven forty-five in the morning. Ate a bowl of rice porridge for lunch, and a dish of Italian pasta for dinner.
Saturday, October 13, 2012
Got up at nine o'clock in the morning. Ate a bowl of noodle soup for lunch, and a Japanese one-pot meal for dinner. Stayed at home for the entire day.
Sunday, October 14, 2012
Got up at nine-thirty in the morning. Ate a bowl of rice porridge for lunch, and a dish of Italian pasta for dinner. It was a warm day with a maximum temperature of 86 degrees F (30.0 degrees C). Stayed at home for the entire day.
Monday, October 15, 2012
Got up at seven forty-five in the morning. Ate a bowl of noodle soup for lunch. Went out shopping at a grocery store this evening. Ate pieces of Central Market's pizza for dinner.
Tuesday, October 16, 2012
Got up at seven forty-five in the morning. Ate a bowl of rice porridge for lunch, and a dish of Italian pasta for dinner.
The graphene FETs don't fully turn off for any gate voltage due to the absence of an energy gap in the graphene band structure. At the so-called Dirac point near Vgs=0V, the drain current is low, leaving holes from the source and electrons from the drain to be recombined in the graphene channel. Obviously, these graphene FTEs aren't appropriate for 'the low power digital logic applications' because of their insufficient Ion-Ioff ratio.
BTW, Why is it called the Dirac point? In solid-state physics, the positive hole is the place in the filled band where the electron is absent from. It's different from the positron, which Professor Paul A. M. Dirac identified in the 1920s. The positron is the first antimatter discovered. Maybe, the Dirac point of the graphene FETs is named after another Dirac.
Wednesday, October 17, 2012
Got up at seven forty-five in the morning. Ate a bowl of noodle soup for lunch, and a Japanese meal for dinner.
It's well known that one of the disadvantages of the bipolar transistors including HBTs is their large size, in spite of their higher drive. Their sizes are typically in the sub-micron range, to my knowledge. In the BiCMOS technology, the bipolar transistors with high drive current are used only for the limited paths in a chip in order to compensate for the disadvantages in size and power consumption while boosting the circuit performance. For instance, a bipolar transistor can be connected to the output buffer of the Inverter, NAND, or NOR logic composing of the MOSFETs in order to boost their Vout driving performance.
On the assumption that the area of a bipolar transistor is 10 times larger than that of a MOSFET when a BiCMOS chip is composed of bipolar transistors and MOSFETs at a one-nine ratio, the size of a BiCMOS chip becomes about 1.9 times larger than that of a MOSFETs chip. When a BiCMOS chip is composed of bipolar transistors and MOSFETs at a five-five ratio, the size of a BiCMOS chip becomes about 5.5 times larger than that of a MOSFETs chip. According to my old knowledge obtained about one decade and a half ago, the advantage of the BiCMOS in terms of the speed fades with reducing the supply voltage, especially when it's reduced below 2.0~2.5V. It seems that the BiCMOS may not be appropriate for consumer electrical appliances including PCs, smartphones, and other gadgets because of its larger size and possibly its higher cost. Probably, the BiCMOS is applicable for the higher voltage appliances in autos, aircraft, RF communication stations, military demands, and so on.
The partial use of the devices, the speed of which is faster than that of the MOSFETs but the size of which are larger, is a practical idea. It seems that, in order to extend the applicability of this technology, the size of the fast devices should be 3 ~ 5X, or hopefully below, relative to a MOSFET.
Thursday, October 18, 2012
Got up at seven forty-five in the morning. Ate a bowl of vegetable soup for lunch, and a dish of Italian pasta for dinner.
There should exist several ideas to remove or to reduce the parasitic capacitances on the top of the multiple-fin FinFETs, without relying on the Tri-Gate structure. A simple idea about the FinFET device structure that enables it to achieve this aim was found long ago. When I was practicing the English speech this morning, a process integration method for it occurred to me. It may be possible. To be honest, however, the practicability of this integration method is uncertain because of the lack of data on the controllability of an anisotropic etch back process necessary for it. I believe that because there is an etch stop layer, an anisotropic etch should be carried out rather controllably. No additional photo litho process step is necessary.
While I'm at it, I also came up with a device structure of the bipolar transistor that allows us to save its area. This idea may help integrate the bipolar transistors into a chip composed of multiple-fin FinFETs while avoiding a significant increase in the size of a chip. However, unlike the multiple-fin FinFETs, the BiCMOS technology may not be suitable for low power/low voltage applications, as written yesterday.
These rambling thoughts prevented me from focusing on the daily speech practice today.
Friday, October 19, 2012
Got up at seven forty-five in the morning. Ate a bowl of rice porridge for lunch, and a dish of Italian pasta for dinner.
The continuous scaling of the dimensions of the multiple-gate MOSFETs by reducing their body thickness is a moderate idea for further improvement in the speed and power consumption of a chip. The use of the Si N-channel and the Ge P-channel to attain the Nch Ion – Pcn Ion ratio = ~1 by utilizing good hole-mobility in the Ge channel may be expected as a reasonable option.
The compound semiconductor channel should be a promising technology for high-performance logic and RF applications, because of excellent carrier mobility. As written previously, for digital logic applications, in order to avoid scaling back the device dimensions by some technology generations because of the high permittivity and the existing device structure oriented toward high carrier mobility (e.g. HEMT), the introduction of it may require the adoption of the technologies that significantly improve the gate length scalability, e.g. the FinFET, Tri-Gate and so on.
The success of the integrated optical interconnects into a CMOS chip depends upon the speed, the power consumption, and the size of the optical devices, which may be partially integrated, bearing resemblance to the HBTs of the BiCMOS technology. The speed of the optical devices for this application needs to be at least comparable to or desirably faster than that of the state-of-the-art MOSFETs. If not, the integrated optical interconnect will never beat the expectation for it. This is a critical condition for the practical implementation of the integrated optical interconnects. The power consumption for the optical device combining a light-emitting device and a phototransistor (or other optoelectronic device) has to be comparable to that of the MOSFET. The total size of the optical device combining a light emitting device and a phototransistor has to be 3 ~ 5X or below larger than that of the MOSFET. Actually, this is a very challenging technology. In other words, it's an idea difficult to accomplish. If the size of the optical device for the integrated optical interconnects were to become comparable to that of the MOSFET while satisfying the other two requirements above, the optical interconnects would be substituted for all the metal interconnects on a chip. It's a dream chip.
Saturday, October 20, 2012
Got up at nine forty-five in the morning. Ate a bowl of noodle soup for lunch, and a Japanese-Western meal for dinner. Stayed at home for the entire day.
Sunday, October 21, 2012
Got up at nine forty-five in the morning. Ate a bowl of rice porridge for lunch, and a Japanese meal for dinner. Stayed at home for the entire day.
Monday, October 22, 2012
Got up at seven-thirty in the morning. Ate a bowl of noodle soup for lunch, and a dish of Italian pasta for dinner.
Tuesday, October 23, 2012
Got up at seven-thirty in the morning. Ate a bowl of rice porridge for lunch. Went out shopping at a grocery store this evening. Ate pieces of California Pizza Kitchen's pizza for dinner.
Wednesday, October 24, 2012
Got up at seven forty-five in the morning. Ate a bowl of noodle soup for lunch, and a dish of Italian pasta for dinner.
Thursday, October 25, 2012
Got up at seven forty-five in the morning. Ate a bowl of rice porridge for lunch, and a Japanese meal for dinner.
Friday, October 26, 2012
Got up at seven forty-five in the morning. Ate a bowl of noodle soup for lunch, and a dish of Italian pasta for dinner. The wind blowing out of the northwest brought a little chill in the air around.
Saturday, October 27, 2012
Got up at eight-thirty in the morning. Ate a bowl of rice porridge for lunch, and a Western-Japanese meal for dinner. Stayed at home for the entire day.
Sunday, October 28, 2012
Got up at nine forty-five in the morning. Ate a bowl of noodle soup for lunch, and a dish of Italian pasta for dinner. Stayed at home for the entire day.
Monday, October 29, 2012
Got up at seven forty-five in the morning. Ate a bowl of rice porridge for lunch. Went out shopping at grocery stores this evening. Ate a Japanese one-pot meal for dinner.
Tuesday, October 30, 2012
Got up at eight o'clock in the morning. Ate a bowl of noodle soup for lunch, and pieces of Central Market's pizza for dinner.
Wednesday, October 31, 2012
Got up at seven forty-five in the morning. Ate a bowl of rice porridge for lunch, and a dish of Japanese meal for dinner.
So far, to my knowledge, the InGaAs is the most desirable compound semiconductor for the N-channel because of the excellence in its electron mobility and the adjustability of its energy band gap. The Ge may be the most appropriate for the P-channel because of its good hole mobility. It seems that the device designs for the multiple-fin FinFET/Tri-Gate utilizing the InGaAs N-channel and/or the Ge p-channel are obvious. However, the difficulty and the complexity of integrating them into a chip still remain. The basic idea of the process integration to accomplish it occurred to me in September 2009.
Without using any compound semiconductor channel, the use of the Si N-channel and the Ge P-channel may be expected as a reasonable idea for the near future IC chip, considering several aspects, e.g. the process simplicity, the production cost, and the environmental protection. Needless to say, both the Si and the Ge are harmless.
As told several times, the completeness of putting out rubbish after separating it into electronic devices containing a small amount of hazardous materials and other items should fix the issue.
