Tuesday, September 1, 2009
Got up at eight o'clock in the morning. Ate a bowl of cereal for lunch. Read several technical papers. Took a break for a bowl of Matcha tea at four o'clock. Today the maximum temperature was 92 degrees F (33.5 degrees C).
Wednesday, September 2, 2009
Got up at eight-fifteen in the morning. Ate a bowl of cereal for lunch, and a Japanese-style meal for dinner. Read a couple of technical papers.
Thursday, September 3, 2009
Got up at seven forty-five in the morning. Ate a bowl of cereal for lunch.
The following is the 2nd part of the overall summary of IEDM 2008:
The table below indicates the basic properties of Si, Ge, and III-V compound semiconductors:
Channel Material Dielectric Constant Energy Band Gap [eV]
Si 12 1.11
Ge 16 0.66
GaAs 13 1.43
InP 14 1.27
InAs 14.5 0.36
InSb 18 0.17
InxGa1-xAs 13~14.5 0.36~1.43
In most of the technical papers concerning non-Si channel MOSFETs in 2008 IEDM, the Ge channel was investigated for high-performance pFETs, and the III-V compound channels such as the GaAs and InGaAs channels were investigated for high-performance nFETs. Unstrained/strained Ge and III-V compound materials offer significantly higher mobility and injection velocities at the virtual source of holes and electrons than the unstrained/strained Si channel, respectively. For surface channel devices, the formation of a good interfacial passivation layer between the High-k gate dielectric (ZrO2, HfO2, Al2O3) and the channel may be necessary in order to reduce the interface state density Dit and to suppress the mobility degradation due to various scattering mechanisms at the interfaces.
For CMOS logic applications, the double-gate device configuration such as a DG-FinFET/TriGate with high-k gate dielectric is probably necessary in order to improve the short channel behavior and the gate length scalability of FETs with higher dielectric constant channels. Moreover, the volume inversion of the DG transistor may also help relax the degradation in mobility due to scatterings near the interfaces between the high-k gate dielectrics and the channel. The Band-To-Band Tunneling of Ge channel pFET is higher than that of the Si channel and has to be overcome by optimizing the device structure. For III-V nFETs, unacceptably high BTBT of InAs or InSb channel nFET seriously limits the device performance, but the BTBT of GaAs channel nFET is comparable to that of Si channel nFET because of its large band gap. In the case of InGaAs, the band gap and BTBT are tunable by changing indium content. Within non-Si channel FETs, the combination of the Ge p-channel and the GaAs/InGaAs n-channel seems to be the most appropriate candidate for DG-FinFET/TriGate.
In some papers, single-gate InAs-/InGaAs-channel transistors such as short-channel HEMT, surface-channel nFETs, or buried-channel nFETs were studied for logic applications. IBM reported, "scaling behavior is investigated experimentally down to (Lg=) 80nm for the first time in III-V nFET". This is for non-CMOS but may also be considered for CMOS logic applications. An In0.7Ga0.3As quantum well layer structure with a peak effective mobility of 3810cm2/Vs is used and its buried channel nFET shows a high drive current of 960uA/um at Vdd=1.0V. The buried channel has an advantage in high mobility because the channel is kept away from scattering centers located near the interface between the high-k gate dielectric and the channel. It also has the other advantage of low gate leakage but it has a disadvantage in scalability. The Ge channel, which is the most promising candidate for non-Si channel pFETs, also has severe problems in the gate length scaling because of its higher dielectric constant. As long as the semiconductor industry continues to maintain the current roadmap for HP CMOS logic applications, the gate length scaling of Si channel CMOS will probably end sometime in the next decade (Lg=10~30nm). The delay in the gate length scaling may be unavoidable. In order to substitute for Si FETs by overtaking it in terms of the circuit speed, the gate lengths of both non-Si channel nFETs and pFETs have to be reduced down the 30nm range or below. It seems that scaling the gate lengths of both single-gate Ge pFETs and single-gate InGaAs nFETs down to the Lg target for the supply voltage of 0.8~1.0V is quite difficult and requires a lot of effort. The use of higher-k gate dielectric such as ZrO2 (dielectric constant 30? or 20~25?) helps scalability to some degree. It goes without saying that the implementation of both Ge pFETs and III-V nFETs on a chip, the low melting point of Ge, and the necessity of the gate first process for high-k/metal gate stack give rise to difficulties and complexities in its process integration obviously.
For non-CMOS future logic applications, the performances of short-channel HEMTs have been reported recently. MIT demonstrated short channel (30nm) E-mode InAs PHEMTs with ft=601 and fmax=608 GHz and logic performance. It demonstrates a source injection velocity of 2.5X10^7cm/s at Vds=0.5V. In the case of non-CMOS, the critical point seems to be placed in the hands of the circuit designers, while making device structure and process integration simpler. It's uncertain whether the supply voltage of 0.5V is low enough to solve a problem in power consumption of non-CMOS or not, though it should help reduce the gate leakage associated with the Schottky metal gate and improve the short channel control. "For HEMT devices, the maximum gate voltage that can be applied is rather low (~0.5V) compared to that of MOSFETs (>1V) due to their high gate leakage associated with Schottky metal gate," IBM reported. "Therefore MOSFET structures are more suitable for digital applications due to their higher drive current as well as lower gate leakage". It seems that the MOSFET structure can be better than the HEMTs structure for digital applications if either a circuit designer finds a new method to reduce the power consumption without either using CMOS or decreasing the supply voltage down to 0.5V, or a process integration engineer finds a practical method to fabricate both Ge pFETs and InGaAs nFETs on a chip for CMOS.
For digital logic applications,
1) InGaAs N-Channel and Ge P-Channel Multiple-Fin FinFETs/TriGates with Low-k Insulating Dielectrics and Supply Voltage of ~1.0V, (Higher Performance and High Scalability, but Higher Cost)
2) InGaAs N-Channel and Ge P-Channel Single Gate MOSFETs with Supply Voltage of ~1.0V, (Higher Performance but Higher Cost)
3) InGaAs MOSFETs and Non-CMOS Low Power Circuits (???) with Supply Voltage of ~1.0V, (Higher Performance and Lower Cost, if possible)
4) InAs HEMTs with Supply Voltage of ~0.5V, (Lower Cost and Higher Scalability, but Lower Performance)
For analog logic applications,
1) InAs HEMTs with Supply Voltage of ~0.5V
Friday, September 4, 2009
Got up at seven-thirty in the morning. Ate a bowl of cereal for lunch, and pieces of Central Market's Pizza for dinner.
Recently, my iMac G5 turned off by itself without any warning several times a day. The condition of my iMac G5 has become worse and worse for the last couple of weeks. It seems that its power supply unit went wrong. According to the information found on a website, this is a known problem that most of the capacitors installed in both the power supply and the logic board units of some personal computers and workstations manufactured by Apple, Dell, HP, and others sometime between 2004 and 2006, including the first and second generations iMac G5, are found to be potentially defective. More exactly speaking, those leaky capacitors were fabricated using shady incomplete materials by parts manufacturers overseas. Apple had offered the iMac repair extension program to its annoyed customers for this issue previously. However, the program was closed in the middle of December 2008.
Saturday, September 5, 2009
Got up at ten o'clock in the morning. Ate a bowl of cereal for lunch. Went out shopping at grocery stores this afternoon. Ate a Japanese-style meal for dinner.
Sunday, September 6, 2009
Got up at ten-thirty in the morning. Ate a bowl of cereal for lunch, and a dish of Spaghetti pasta for dinner. Read several technical papers.
Monday, September 7, 2009
Today is Labor Day. Got up at eight-fifteen in the morning. Ate a bowl of cereal for lunch, and a Japanese-style meal for dinner. Read several technical papers.
The following shows the patents in which my name is listed as either an inventor or a co-inventor:
[1] An Embedded DRAM Structure and Method of Formation (SC91127A)
Motorola, Inc.
Shiho Y., Barron C. C.
[2] Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing (20050250287)
Freescale Semiconductor, Inc.
Chen J., Mora R. R., Rossow M. A., Shiho Y.
[3] Method for making a semiconductor device with strain enhancement (7282415)
Freescale Semiconductor, Inc.
Zhang D., Nguyen B., Thean V., Shiho Y., Dhandapani V.
[4] Self correcting suppression of threshold voltage variation in fully depleted transistors (20060240629)
Freescale Semiconductor, Inc.
Orlowski M., Shiho Y.
The following also shows the publications in which my name is listed as either an author or a co-author:
[5] Moderately Doped Channel Multiple-FinFET for Logic Applications
Shiho Y., Burnett D., Orlowski M., Mogab J.
2005 IEDM Technical Digest, 5-7 Dec. 2005, Page(s): 997-1000
[6] Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement
Zhang,D., Nguyen,B.Y., White T., Goolsby B., Nguyen T., Dhandapani,V., Hildreth J., Foisy M., Adams V., Shiho Y., Thean A., Theodore D., Canonico,M., Zollner S., Bagchi S., Murphy S., Rai R., Jiang J., Jahanbani M., Noble R., Zavala M., Cotton R., Eades D., Parsons S., Montgomery P., Martinez A., Winstead B., Mendicino M., Cheek J., Liu J., Grudowski P., Ranami N., Tomasini P., Arena C., Werkhoven C., Kirby H., Chang C.H., Lin C.T., Tuan H.C., See, Y.C., Venkatesan, S., Kolagunta, V., Cave, N., Mogab, J.
VLSI Technology Digest of Technical Paper 2005 Symposium, 14-16 June 2005, Page(s): 26-27
[7] Challenges for the integration of metal gate electrodes
Schaeffer J.K., Capasso C., Fonseca L.R.C., Samavedam S., Gilmer D.C., Liang Y., Kalpat S., Adetutu,B., Tseng H.-H., Shiho Y., Demkov A., Hegde R., Taylor W.J., Gregory R., Jiang J., Luckowski E., Raymond M.V., Moore K., Triyoso D., Roan D., White Jr B.E., Tobin P.J.
2004 IEDM Technical Digest, 13-15 Dec. 2004, Page(s): 287-290
[8] Optimization of Sub-50nm MOSFETs to Mitigate Drive Current Degradation Due to Silicon Recess in S/D
Shiho Y., Winstead B., Foisy M., Orlowski M.,
Simulation of Semiconductor Processes and Devices 2003, Sept. 3-5 2003, Page(s): 1 -2
[9] Hot carrier reliability considerations in the integration of dual gate oxide transistor process on a sub-0.25 _m CMOS technology for embedded applications
Bhat N., Chen P., Tsui P., Das A., Foisy M., Shiho Y., Higman J., Nguyen J.-Y., Gonzales S., Collins S., Workman D.
Electron Devices Meeting, 1998. Technical Digest, 6-9 Dec. 1998, Page(s): 931 -934
[10] A 100 nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications
Yeap, G.C.-F., Chen, J., Grudowski, P., Jeon, Y., Shiho, Y., Qi, W., Jallepalli, S., Ramani, N., Hellig, K., Vishnubhotla, L., Luo, T., Tseng, H., Du, Y., Lim, S., Abramowitz, P., Reddy, C., Parihar, S., Singh, R., Wright, M., Patterson, K., Benavides, N.
VLSI Technology Digest of Technical Papers 2002 Symposium, 11-13 June 2002, Page(s): 16–17
[11] Effects of SOI film thickness on high-performance microprocessor by 0.13/spl mu/m partially-depleted SOI CMOS technology
Yang J., Min B. W., Yasuhito, S. (Shiho Y.), Kang L., Walker P., Mendicino M., Yeap G., Foisy M., Cox K., Cartwright J., Venkatesan S.
SOI Conference, 2003. IEEE International, Sept. 29 - Oct. 2, 2003, Page(s): 41 –42
Degrees of my contributions to these patents and publications vary, depending on who the first inventor/author is. My contributions to the patent [1] and publications [5][8], in which my name is put as either the first inventor or the first author, are above 90% surely. Both co-inventors and coauthors contributed to these works in document proofreading, software calibration, and so on.
The photo on the right was originally taken for
the renewal of my ID badge about ten years ago.
Tuesday, September 8, 2009
Got up at eight o'clock in the morning. Ate a bowl of cereal for lunch, and a dish of Italian pasta for dinner. Read a couple of technical papers.
Wednesday, September 9, 2009
Got up at seven-thirty in the morning. Ate a bowl of cereal for lunch, and a Japanese-style meal for dinner. Read several technical papers.
Thursday, September 10, 2009
Got up at eight-fifteen in the morning. Ate a bowl of cereal for lunch, and a Japanese-style meal for dinner.
Friday, September 11, 2009
It's a rainy day. Got up at seven forty-five in the morning. Ate a bowl of cereal for lunch.
Replaced the broken power supply unit of my iMac G5 this afternoon. It seems that the excess heat generated by leaking capacitors in the power supply unit for the last couple of months did not cause any noticeable damage to the system board, fortunately. Unusual behaviors of iMac G5, such as sudden turnoffs of the power supply unit and incessant operating of the cooling fan, have cleared up. Indeed, it's still uncertain whether the new power supply unit has durable fine capacitors or not.
Ate pieces of a California Pizza Kitchen's pizza for dinner.
Saturday, September 12, 2009
It's a rainy day. Got up at ten-fifteen in the morning. Ate a bowl of cereal for lunch, and a bowl of Japanese noodles for dinner. Stayed at home for the entire day.
The following diagram indicates my idea of the process integration method enabling Ge pFETs and III-V nFETs on a chip.
As a starting material, the wafer of the InGaAs film on the Si substrate formed by using a wafer bonding technique is used [1]. Throughout the integration steps, the formation of dislocations due to the thermal expansion mismatch stress has to be minimized. Some researchers have demonstrated previously that the removal of InP substrate from temporarily bonded wafers (Si, InGaAs-InP) prior to the thermal annealing to achieve covalent bonding helps reduce defect formation. Following a cleaning process, the 10~20nm thick InGaAs channel layer is epitaxially grown on the wafer [2]. The SiO2 Trench Isolations are formed in the areas between the nFETs regions and the pFETs regions [3]. The nFETs regions are covered with the hard mask such as the Si3N4 film. The InGaAs layers are etched away from the uncovered pFETs regions. After a cleaning step, the graded SiGe buffer layer is selectively and epitaxially grown on the exposed Si substrate in the pFETs region, and then the Ge channel layer is also selectively and epitaxially grown on it, followed by the hard mask removal [4]. Here, in-situ sequential clean and epi-growth processes are preferable. This process integration scheme is followed by the gate-first process with a lower thermal budget. The temperature of later processing steps has to be kept below the melting point of Ge (958.5 degrees C).
This scheme brings several benefits in cost and manufacturability. The use of the InGaAs-Si bonded wafer may be cost-effective. The indium content of the InGaAs channel can be adjusted, and the InAlAs barrier layer on the InGaAs channel and/or the Si cap layer on the Ge channel for buried channel options can be formed in-house. The Ge channel receives lower Dt so that the Ge out-diffusion during annealing steps can be minimized. The presence of the graded SiGe buffer layer controls the biaxial compressive strain in the Ge channel and suppresses the formation of defects. The insulations beneath the bottom of the SiO2 trench isolations, which extend to the Si substrate, are known to be reliable. This process integration method is practical only if the thickness of the InGaAs buffer layer required to maintain good quality of the crystallization in the InGaAs channel can be comparable to the depth of the trench isolation, and the thermal budget of transistor processing steps can be kept low enough to avoid the unacceptable defect formation due to the thermal expansion mismatch stress. Instead of using a wafer bonding technique, the formation of multiple III-V compound buffer layers using CVD at a temperature of 400~700 degrees C should be an optional choice; however, it probably requires tinker total thickness of buffer layers.
This integration method looks easy, but the control of defects in this system is quite difficult. Again, this process integration method enables the fabrication of both Ge channel single-gate pFETs and III-V compound channel single-gate nFETs on a chip for CMOS logic applications. The most difficult point in terms of its process integration is the formation of superior InGaAs channel film on the Si substrate. The most difficult point in terms of its device characteristics is the gate length scalability of pFETs.
Sunday, September 13, 2009
Got up at nine-fifteen in the morning. Ate a bowl of cereal for lunch. Went out shopping at grocery stores this afternoon. Ate a dish of Japanese pasta for dinner.
Monday, September 14, 2009
Got up at seven forty-five in the morning. Ate a bowl of cereal for lunch, and a Japanese-European-style meal for dinner. Read a couple of technical papers.
Tuesday, September 15, 2009
Got up at seven forty-five in the morning. Ate a bowl of cereal for lunch, and a dish of Italian pasta for dinner. Read a couple of technical papers.
Today, my new ideal on the process integration method enabling Ge p-channel single-gate pFETs and III-V n-channel single-gate nFETs on a chip for high-performance CMOS logic applications was found again. This idea is better than that identified on September 12, 2009. It seems that, in this idea, there is no serious difficulty in growing epitaxially a perfect InGaAs channel film on the Si substrate.
My new ideal on the process integration method enabling Ge p-channel multiple-fin DG-FinFETs/TriGates and III-V n-channel multiple-fin DG-FinFETs/TriGates on a chip for future high-performance CMOS logic applications was also found. In this idea, the problem of achieving highly scalable Ge p-channel transistors is also solved, as written previously. It seems to me that the latter idea is unique enough to obtain a patent for an invention. This idea will not be written in any file because of confidentiality reasons for a while. Sometime in the future, this invention will be applied for a patent.
Wednesday, September 16, 2009
Got up at eight-fifteen in the morning. Ate a bowl of cereal for lunch, and a Japanese-style meal for dinner. Read a couple of technical papers.
Today, the brief explanations of my main patent and publications are given as follows:
An Embedded DRAM Structure and Method of Formation (SC91127A)
Motorola, Inc.
Shiho Y., Barron C. C.
The patent SC91127A, in which my name is listed as the first inventor, was invented in 1997 and issued in 2001. My inventions of a unique asymmetrical device structure of DRAM pass-transistor may enable to scale the size of embed DRAM cell. A co-inventor contributed to this work in document proofreading.
Optimization of Sub-50nm MOSFETs to Mitigate Drive Current Degradation Due to Silicon Recess in S/D
Shiho Y., Winstead B., Foisy M., Orlowski M.,
Simulation of Semiconductor Processes and Devices 2003, Sept. 3-5 2003, Page(s): 1 –2
The technical paper above, in which my name is listed as the first author, was published in the 2003 SISPAD Proceeding. My presentation was given in a ballroom of Boston Marriott Cambridge, MA in September 2003. My research on this subject has been done from 2000 through 2003. My study predicted that the recess of silicon in the Source/Drain and Extension area severely compromises the performance of sub-50nm MOSFETs, and revealed that the silicon recess due to over-etching must be kept at a minimum and careful tuning of S/D, halo, and silicide engineering is required to mitigate the drive current degradation due to silicon recess in S/D.
One year before my research on this subject began, a coworker briefly investigated it in 1999. However, his conclusion was quite different from mine. His study concluded that the silicon recess does not deteriorate the MOSFET performance if the depth of it is kept within a few hundred angstrom. Since then until my study, the silicon recess had been ignored because of his result. Indeed, actual devices with the silicon recess of a few hundred angstroms show very severe degradation in the MOSFET performance. Even the recess of tens angstrom degrades the FET performance significantly.
Moderately Doped Channel Multiple-FinFET for Logic Applications
Shiho Y., Burnett D., Orlowski M., Mogab J.
2005 IEDM Technical Digest, 5-7 Dec. 2005, Page(s): 997-1000
The technical paper below, in which my name is listed as the first author, was published in the 2005 IEDM Proceeding. My speech was given in the ballroom of Hilton-Washington DC in December 2005. In this paper, Moderately Doped Channel (MDC) Multiple-FinFET is proposed and its electrical characteristics are investigated using TCAD simulations. It is shown that the MDC offers a better immunity to variations of the fin profile than the undoped channel for a short channel device, and Multiple-fin FinFET is critical to logic applications.
When the double gate SOI device was devised a couple of decades ago, its channel was doped. In the 1990s, the undoped channel became standard for thin film SOI, including double-gate and FinFET, when the variations of the transistor characteristics due to random dopant fluctuation in the channel became non-negligible with scaling down the transistor dimension. My study suggested that maintaining the effective width of multiple-fin FinFET wide enough helps suppress the variations in the transistor characteristics.
Needless to say, the patent above was filed and the publications above were submitted to the conference committees after passing through a number of required approval steps.
Thursday, September 17, 2009
Got up at eight o'clock in the morning. Ate a bowl of cereal for lunch, and a Japanese-style meal for dinner.
The Democratic Party of Japan won the election on August 30, 2009. The 93rd Prime Minister of Japan was appointed as designated by the Diet on September 16, 2009. The Prime Minister, Mr. Yukio Hatoyama, Ph.D. formed a new cabinet.
Friday, September 18, 2009
Got up at eight o'clock in the morning. Ate a bowl of cereal for lunch, and pieces of Central Market's pizza for dinner.
Saturday, September 19, 2009
Got up at eight forty-five in the morning. Ate a bowl of cereal for lunch, and a Japanese-style meal for dinner. Stayed at home for the entire day.
Sunday, September 20, 2009
Got up at five forty-five in the morning. Read online news. Went to bed about seven o'clock and got up again at ten o'clock. Ate a bowl of cereal for lunch. Went out shopping at grocery stores this afternoon. Ate a dish of Italian pasta for dinner. We haven't seen any movie since February 7, 2009, and haven't watched any TV program since February 22, 2009, either.
On 23 June 2009, there was a strange incident. There was an abrupt sound of a violent explosion around my house in the morning that day. The cause of the sound was unknown.
Recently, my wife found a hole in the window screen of her room. She told me that somebody might throw a stone at the window of her room on 23 June. Someone might shoot an air gun, a slingshot, or something else. Fortunately, that attempt did not break any glass of the window because either a stone or a plastic/lead bullet hit the window covered with the window screen. It was also fortunate that my wife slept on the bed in the other room at the time of the incident.
As written in my diary on July 1, 2009, about a week after that incident, a white girl who stood before me in the queue to pay bought two glass plates at Lowe's that afternoon. This was written in my diary because her acting was strange and suspicious. It seems that a political group, a religious group, a girl's group, or an ethnic group tried to vent their anger on us by doing it.
My wife sent me a couple of emails regarding different topics on15, 16, and 21 of June 2009. Those emails tell about "the Japanese Seniority System", "Religion" and "Tricks". One, two, or all of her emails might provoke their action above. There are always Asian agitators hidden behind the scenes.
Looking back to the past, there were several similar incidents previously. As written on May 11, since1999 through 2006, my pickup truck had several times gotten nails in its tires. In the summer of 2006, we decided that our vehicles should be kept in the garage of our house when we are at home. Our vehicles have never gotten any puncture since then. In July 2005, someone who drove a dark SUV ran into my wife's car and then drove off when her car stopped at an intersection.
It seems that there exist groups that tend to commit violent acts here. They may justify themselves by saying that these acts were intended for tests. Indeed, false accusations and unjustified resentments led them to barbarism. My wife told me that it was old men who were behind their violent acts.
Monday, September 21, 2009
Got up at seven o'clock in the morning. Ate a bowl of cereal for lunch, and a Japanese-style meal for dinner. Read a technical paper.
Needless to say, my gender is male. My favorite color isn't purple. It's blue. For the purpose of calming myself with aromatherapy, bowls of lavender potpourris have been always placed on the desk at the office, and on the desks, chests, and tables of my house since 1997 until now. Lavender is used as a base in many men's colognes, as well known.
BTW, I realized a couple of years ago that the reduction in weight helps control my emotions more effectively than aromatherapy does, in my case. Yesterday, an event reminded me of it.
Tuesday, September 22, 2009
Got up at seven-thirty in the morning. Ate a bowl of cereal for lunch. Wire-transferred ¥325,000 to a Japanese Scholarship Foundation for the completion of the return of a scholarship loan this morning. The return of the total scholarship loan of ¥3,825,000 will be completed this week or early next week. It took fifteen years. Attached above is the photocopy of the wire transfer form used in this transaction.
My wife, Naoko Shiho, is a Japanese. Both her parents are Japanese. Her maiden name is Kobayashi and her birthplace is Chino-shi, Nagano-ken, Japan. Chino, CA isn't a sister city of her birthplace. It's in Longmont, CO.
Before overwork (or something else) preyed on my health condition in 2003, my daily meals had included a few glasses of milk, protein, and creatine supplements in order to make workouts more effective from 1997 until 2002. Both protein and creatine supplements are known to help gain muscle mass. These supplements are sold at most grocery stores in the US. The uses of protein and creatine supplements aren't considered doping and aren't banned by the majority of sports organizations. Several bottles of these supplements were kept on my desk those days.
One day in 1999 or 2000, either a company nurse or a human resource manager called me to the nurse's room suddenly and gave me a surprise drug test. The result of the test was negative. It must be negative because any illegal thing has never attracted my interest in my life. Even a cigarette hasn't drawn my attention at all. It seems to me that someone spread a trivial rumor about the reason of my toughness those days. These supplements don't improve mental durability, indeed.
During our travel by truck around the Big Bend National Park and the White Sands National Park in the early summer of 2003, the presentations of not only our passports but also our visas or green cards were required at some checkpoints in Texas and New Mexico. Because we were not carrying our AOS cards during the travel, an inspector of Immigration organizations in the US such as INS might telephone a company in order to verify our permanent resident statuses. With this as a start, a group might spread a malicious rumor about us, as they always do.
Wednesday, September 23, 2009
It's a rainy day. Got up at eight o'clock in the morning. Ate a bowl of cereal for lunch, and a Japanese-style meal for dinner. Read a technical paper.
There is no doubt that some groups have been listening in to our daily conversation at home, tapping our telephone lines, tracing our internet access, hacking our computers, and following our vehicles. They have been doing those spying activities for the purpose of making decisions, finding ammunition to attack me, and so on. It has been revealed gradually that some Americans who have cooperated with these groups tend to let me know the fact that they have been listening to my conversations as if not so intended. It's still uncertain whether they have been trying to inform me of the facts with good intentions or not. However, it's very sure that most of them have been doing it for their benefit with ill will.
They usually ignore my words that are inconvenient for them. In most cases, they only use my words out of context that are convenient for them in order to trip me up. They also use the words that somebody else says near me as if those were my words. This is one of the diversionary tactics often seen around me.
It seems that they used my words out of context to trip me up on Monday, September 21. They told me so indirectly by making a crank call just after that.
This is one of the Asian-style swindles. Similar fraud may be also found in the West.
Thursday, September 24, 2009
It's a rainy day. Every time it rains it gets colder. Got up at eight-fifteen in the morning. Ate a bowl of cereal for lunch, and a Japanese-style meal for dinner.
It took me about three hours to reach the customer service of a Japanese Scholarship organization at their phone number only for calls from overseas. At about two a.m. by CST, over the telephone, he said, a voucher for the completion of the return of a scholarship loan would be sent to my legal domicile in Japan within a few months after a Japanese Scholarship organization receives ¥325,000 from me. My mother will transfer the voucher to my home address in the US.
Friday, September 25, 2009
Got up at eight-thirty in the morning. Ate a bowl of cereal for lunch, and pieces of California Pizza Kitchen's pizza for dinner.
The following describes my personal opinion on the High-Performance Logic Transistor Roadmap:
The physical thickness of the SiON gate dielectric of the FETs that IBM demonstrated in a paper of 2008 IEDM is 1.15nm. Its EOT may be in the range of 1.05nm ~ 1.15nm because the increase in the dielectric constant by substituting a SiO2 film with a SiON film is known to be minor. Therefore, taking the poly depletion and quantum effects into consideration, its inversion thickness (Tinv) can be roughly estimated to be about 1.5nm.
It seems that the scaling limit of Tinv of the SiON/PolyGate stack is about 1.5nm. On the other hand, the scaling limit of EOT of the High-k film is 0.5nm ~ 0.7nm and that of Tinv of the High-k/MetalGate stack is 0.7nm ~ 0.9nm. The scaling of the High-k gate dielectric film is limited by the presence of the interlayer (SiON or SiO2), the thickness of which is ~0.5nm. The interlayer isn't dispensable because of the mobility and reliability concerns and isn't scalable because of the fact that the atomic constant of Si is 0.543nm. The choice of other higher-k dielectric materials does not help scale beyond this limit. This fact reminds us how immense the contribution of the SiO2 gate dielectric film to the semiconductor industry was. The SiO2 has been used as the gate dielectric film in the range of the thickness from ~100.0nm down to 1.8nm for several decades, as well known.
Gate Dielectric Film EOT Range Used/ Required
SiO2 ~100.0nm -> 1.8nm
SiON 1.8nm -> 1.1nm
High-k 1.1nm -> 0.7nm or 1.1nm -> 0.6nm
(e.g. HfSiON, HfO2, ZrO2)
The SiON has been used as the gate dielectric film in the range of the EOT from ~1.8nm down to ~1.1nm. The substitution of the SiON/PolyGate stack with the High-K/Metal Gate stack enables the reduction of the scaling limit of Tinv from 1.5nm down to 0.7nm ~ 0.9nm, by both reducing the EOT by a maximum of 0.5nm and removing the poly depletion. However, it should degrade carrier mobility by ~10% for a low-power application and by ~20% for a high-performance application.
On the assumption that this IBM device has the minimum dimensions of the FETs with the SiON/PolyGate stack, a simple scaling rule leads to the result that the possible minimum gate length of the FETs with the High-k/MetalGate stack is Lg = 35X(0.9/1.5) ~ 35X(0.9/1.5) = 16.3 ~ 21nm. According to the current ITRS roadmap for high-performance logic applications, the technology node corresponding to this range of gate length is 40nm (2011), 36nm (2012), 32nm (2013), or 28nm (2014). In this way, the scaling of the gate length will stop in the next five years.
In order to keep the Si channel FETs in existence in leading-edge high-performance logic technology, the delay in the gate length scaling may be unavoidable. For instance, the target gate lengths may be revised from 18nm, 14nm, and 10,7nm to 30nm, 25nm, and 20nm for the technology nodes of 32nm (2013), 22nm (2016), and 16nm (2019), respectively. Instead, performance boosters such as Si(110) wafer, embedded SiC S/D for nFET, or something else will be adopted in order to compensate for the loss in the performance gain obtained from the gate length reduction with them.
When nothing that can be done is left for the Si channel planar FETs, the device structure may be switched to multiple-fin DG-FinFETs/TriGates in the early stage of 2020. Next, the material for the p-channel will be switched from Si to Ge. Then, the material for the n-channel will be switched from Si to III-V compound InGaAs. The gate length may be further scaled from 20nm down to the range of 10nm ~ 16nm by thinning the channel thickness in the 2020s.
At the end of this scenario, my age will be about 65 years old. It seems that further forecasting isn't necessary for quite some time. If the current ITRS Roadmap must be kept, the development of multiple-fin DG-FinFETs/TriGates or something else has to be accelerated intensively.
Saturday, September 26, 2009
Got up at ten o'clock in the morning. Ate a bowl of cereal and a piece of pizza for lunch. Went out shopping at grocery stores this afternoon. Ate a Japanese-style meal for dinner.
Sunday, September 27, 2009
Got up at nine o'clock in the morning. Ate a bowl of cereal for lunch, and a hamburger meal for dinner.
The following story tells about a malicious rumor about a mysterious man:
During the lunch at a picnic area by Lake Travis in Austin Texas in the early summer of 2001, two Japanese women talked about the rumor that some members of the Japanese Organization in Austin were spreading slanders against a man. It seemed to me that two women spoke for the ears of another person. According to their conversation, some members of the Japanese Organization injured his reputation by calling him a ra**st. It's uncertain which a word is, either ra**st or the other ra**st. Whether a slander was true or not was unknown. Who a man is was ascertained, either.
One day a couple of months after the picnic, my attendance at a picnic that the Japanese Organization held was scheduled. A coworker told me that it would be wise for me to keep away from the Japanese Organization in Austin because an unpleasant experience may be waiting for me. That was a suggestive remark. The other troublemaking former coworker encouraged me to come closer to them. What coworkers told me whetted my curiosity those days.
In the mid-summer of 2001, conversations with some members of the Japanese Organization let me realize that some of them were the sources of groundless rumors and they were intentionally spreading slanders against the opposition whom they got mixed up with somebody else. Both Asian groups and American groups were pulling the strings behind them for the acquisition of positions. My decision about my stance on this issue was reached on that occasion, leaving the matter ambiguous. Since then, according to my judgment, my relationship with the Japanese Organization in Austin has been completely stopped, without causing any trouble. Needless to say, the slander above does not concern me at all, to my knowledge.
It seems that a minority group in Japanese industries, American groups relying on credentialism, and other Asian groups tend to be closely interdependent. Asian women's groups and American groups claim feminism and liberation help each other, but, on other occasions, they are at enmity with each other. Senior American groups have been seeking help from the Asian seniority system, while ignoring inexpedient parts of Asian society, such as a mandatory retirement system (at 60 years old) and a lifetime employment system (until a mandatory retirement). Some American groups try to gain a profit by cloaking their actions under philanthropic garb. Feelings of bitter and political intrigues swirled around here and there, behind the scenes. As written previously, these dark feelings in a city led them to barbarism. Criminals are hidden in the crowds.
Monday, September 28, 2009
Got up at eight-thirty in the morning. Ate a bowl of cereal for lunch, and a dish of Italian pasta for dinner.
The following sentences are copied from the letter about "rumor control" that my wife sent me on April 30, 2009.
Some people who had experienced great hardship have written the memoir. A famous person's wife is one of them. I feel sorry about what happened to her.
My husband always tells me whatever happened to him, except classified information about business. For example, when he visited D.C. to attend a kind of meeting and gala, he told me over the telephone that a strange woman spoke to him in the hotel lobby. I'm happy that he is not such a man to fall into a trap.
By the way, in the summer of 2005, my husband and I invited a female Japanese student who stayed in Austin as an intern for dinner at a restaurant and it was all what happened.
--------Naoko Shiho
My wife is right. Extramarital sex has never attracted my attention. A habit of being unfaithful will never be developed.
Tuesday, September 29, 2009
Got up at eight-thirty in the morning. Ate a bowl of cereal for lunch, and a Japanese-style meal for dinner.
There exist many capacitors in the MOSFETs structure. The main capacitances that predominantly control the logic circuit performance are the gate capacitances, the miller capacitances, and the S/D junction capacitances. The capacitance that is unintentionally taken into the FET structure is called the parasitic capacitance. The 3D device structures such as FinFET or Trigate are generally known to have more parasitic capacitances than the planar device structures. The figures below indicate the extra parasitic capacitances found in the multiple-fin DG-FinFET/TriGate structure. The extra parasitic capacitances located on the tops of the fins can be easily deleted by adopting the Trigate structure. The other extra parasitic capacitances found between the gate and the S/D of the multiple-fin DG-FinFET/TriGate structure are similar to those of the planar FETs with the elevated S/D. Adopting low-k insulating dielectric material such as Aurora can reduce these parasitic capacitances, by 38% compared with SiO2. When a lower-k insulating material is identified in the future, the parasitic capacitances can be reduced further.
Figures: Multiple-fin DG-FinFET/TriGate at vertical
cross sections and horizontal cross sections.
Wednesday, September 30, 2009
Got up at seven-thirty in the morning. Ate a bowl of cereal for lunch, and a bowl of Japanese noodles for dinner.
When an Asian-style swindle was commented upon in my diary on September 23, a past incident crossed my mind. In late 1999 or 2000, a Japanese man might use my words out of context that was convenient for him in order to trip me up. He asked me in Japanese, "Do you return to Japan by year's end." My answer in Japanese was, "Yes. I will visit my hometown in Japan during the Christmas holiday."
Since then, some of my coworkers have told me, "I heard that you would go back to Japan." My answer was, "No. Who said that?" They didn't tell me who said so. It seems that they had already known that trick. It reminded me that he introduced himself as the man who had gotten along somehow with smooth-double-tongue at our first meeting.
The means above may be also a type of Asian unscrupulous maneuvers. Following either a nasty trick or a spy operation, he tells an empty lie and spreads a groundless rumor. It's recently a common observation that American groups claiming feminism and liberation tend to commit a Mephistophelean way to lead their opponents astray. It's uncertain which the origin of this sort of maneuver is, the West or the East. What rubbish tricks they use!
